Mind Reach

  Booth algorithm gives a procedure for  multiplying binary integers  in signed 2’s complement representation  in efficient way , i.e., less number of additions/subtractions required. It operates on the fact that strings of 0’s in the multiplier require no addition but just shifting and a string of 1’s in the multiplier from bit weight 2^k to weight 2^m can be treated as 2^(k+1 ) to 2^m. As in all multiplication schemes, booth algorithm requires examination  of the multiplier bits  and shifting of the partial product. Prior to the shifting, the multiplicand may be added to the partial product, subtracted from the partial product, or left unchanged according to following rules: The multiplicand is subtracted from the partial product upon encountering the first least significant 1 in a string of 1’s in the multiplier The multiplicand is added to the partial product upon encountering the first 0 (provided that there was a previous ‘1’) in a string of 0’s in th...

  The adder produce carry propagation delay while performing other arithmetic operations like multiplication and divisions as it uses several additions or subtraction steps. This is a major problem for the adder and hence improving the speed of addition will improve the speed of all other arithmetic operations. Hence reducing the carry propagation delay of adders is of great importance. There are different logic design approaches that have been employed to overcome the carry propagation problem. One widely used approach is to employ a carry look-ahead which solves this problem by calculating the carry signals in advance, based on the input signals. This type of adder circuit is called a carry look-ahead adder. Here a carry signal will be generated in two cases: Input bits A and B are 1 When one of the two bits is 1 and the carry-in is 1. In ripple carry adders, for each adder block, the two bits that are to be added are available instantly. However, each adder block waits for the c...

  The IEEE Standard for Floating-Point Arithmetic (IEEE 754) is a technical standard for floating-point computation which was established in 1985 by the   Institute of Electrical and Electronics Engineers (IEEE) . The standard addressed many problems found in the diverse floating point implementations that made them difficult to use reliably and reduced their portability. IEEE Standard 754 floating point is the most common representation today for real numbers on computers, including Intel-based PC’s, Macs, and most Unix platforms. There are several ways to represent floating point number but IEEE 754 is the most efficient in most cases. IEEE 754 has 3 basic components: The Sign of Mantissa – This is as simple as the name. 0 represents a positive number while 1 represents a negative number. The Biased exponent – The exponent field needs to represent both positive and negative exponents. A bias is added to the actual exponent in order to get the stored exponent. The Normalised ...

  Block Diagram of  Combinational Logic Circuit :   Points to Remember on Combinational Logic Circuit: Output depends upon the combination of inputs. Output is a pure function of present inputs only i.e., Previous State inputs won’t have any effect on the output. Also, It doesn’t use memory. In other words, OUTPUT=f(INPUT) Inputs are called Excitation from circuits and outputs are called Responses of combinational logic circuits. Classification of Combinational Logic Circuits:   1. Arithmetic: Adders Subtractors Multipliers Comparators 2. Data Handling: Multiplexers DeMultiplexers Encoders and Decoders 3. Code Converters: BCD to Excess-3 code and vice versa BCD to Gray code and vice versa Seven Segment Design of Half Adders and Full Adders: A combinational logic circuit that performs the addition of two single bits is called Half Adder. A combinational logic circuit that performs the addition of three single bits is called Full Adder. 1.  Half Adder :   It ...